Field of the Invention
This application is the U.S. national phase entry of PCT patent application no, PCT/EP2014/072717, which was filed on Oct. 23, 2014, which claims the benefit of EP patent application no. 14150722.8, which was filed on Jan. 10, 2014, and which is incorporated herein in its entirety by reference.
The present invention relates to a method for determining overlay errors in a lithographic apparatus. The present invention further relates to methods of manufacturing devices using lithographic apparatus calibrated by such a method, and to data processing apparatuses and computer program products for implementing parts of such a method
Background Art
A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g., comprising part of, one, or several dies) on a substrate (e.g., a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction.
A key performance parameter of the lithographic process is the overlay error. This error, often referred to simply as “overlay” is the error in placing a product features it the correct position relative to features formed in previous layers. As device structures become every smaller, overlay specifications become ever tighter.
Currently the overlay error is controlled and corrected by means of methods such as advanced process control (APC) described for example in US2012008127A1 and wafer alignment models described for example in US2013230797A1. The advanced process control techniques have been introduced in recent years and use measurements of metrology targets applied to substrates alongside the applied device pattern. These targets allow overlay to be measured using a high-throughput inspection apparatus such as a scatterometer, and the measurements can be used to generate corrections that are fed back into the lithographic apparatus when patterning subsequent substrates. The inspection apparatus may be separate from the lithographic apparatus. Within the lithographic apparatus wafer alignment models are conventionally applied based on measurement of alignment marks provided on the substrate, the measurements being as a preliminary step of every patterning operation. The alignment models nowadays include higher order models, to correct for non-linear distortions of the wafer. The alignment models may also be expanded to take into account other measurements and/or calculated effects such as thermal deformation during a patterning operation.
While alignment models and advanced process control have brought great reductions in overlay, not all errors are corrected. Some of these errors may be uncorrectable noise, for example, but others are correctable using available techniques in theory, but not economically correctable in practice. For example, one can envisage yet higher order correction but these in turn would require a higher spatial density of position measurements. The alignment markers/overlay targets occupy space on the substrate and are placed at specific locations, mainly in the scribe lanes between product areas. Deformations of the wafer grid in non-sampled areas (e.g. areas where ICs are printed) may be different than sampled areas. To increase the spatial density and/or measurement frequency of alignment marks and overlay targets would adversely affect both throughput of the lithographic process (wafers per hour) and the functional device area available on each substrate.